Technical Field
The present invention relates to semiconductor devices and, more particularly, to forming airgap spacers without compromising high-k gate dielectric integrity.
Description of the Related Art
As semiconductor fabrication processes improve and the pitch of contacts reduces, an increase in parasitic capacitance between the source and drain contacts of a field effect transistor (FET) results due to thinning of the dielectric spacers between the contacts. Airgap spacers are used to reduce the parasitic capacitance.
In forming conventional airgap spacers, a sacrificial spacer is first formed on the gate sidewalls to protect the gate during downstream processes such as source/drain epitaxy and contact formation. The sacrificial spacers are then removed and replaced to create a gap between the gate and the source/drain contacts.
Spacer removal in this flow is usually a timed etch process. If the spacer etch is too aggressive, the etch may reach to the gate dielectric in the channel region and cause unreliability in the gate dielectric. If the spacer etch is too conservative, the airgap spacer that is produced is too short and the reduction of the parasitic capacitance is less strong. This imprecision makes conventional airgap spacers inadequate for use in small-scale device.